Conventional memory sense amplifiers (sense amps) may include a set of transistors that each are used to connect one or more bit lines to the sense amp. This may be done by connecting a bit line and the sense amp to the source and drain, respectively, of a connecting xe2x80x9cpassxe2x80x9d transistor. A dedicated enable signal may then be connected to the gate of each pass transistor to control which of the bit lines is connected to the sense amp. One potential drawback of this configuration may be that while a particular bit line is connected to the sense amp, the sense amp xe2x80x9cdrivesxe2x80x9d the bit line through the source and drain of the transistor. Due to the amount of capacitance that may be associated with a particular bit line, this may result in significant power consumption through the sense amp.
Additionally, conventional sense amps may also include a single enable transistor that may be used to enable the entire sense amplifier by connecting the sense amp to a power supply voltage, typically ground. By timing when the individual bit lines are connected to the sense amp with respect to when the sense amp enable transistor connects the sense amp to ground, the power consumption due to the driving of a bit line by the sense amplifier, as discussed above, may be reduced. However, this power savings typically comes with the expense, complexity, and power consumption associated with the additional control logic that performs this timing. In addition, such timing circuits may impose the limitation that the bit line enable signals be provided before the sense amp enable transistor is activated. This limitation may undesirably complicate the design of the sense amp and impose difficult timing restrictions on the operation of the circuit.
Thus, there is a continuing need for better ways to improve the power consumption and operation of sense amps.